Reliably producing submicron and smaller features is a key technology for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, as the miniaturization of circuit technology is pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of the VLSI and ULSI technology demand precise processing of high aspect ratio features, such as vias and other interconnects.
As circuit densities increase for next generation devices, the widths of interconnects, such as vias, trenches, contacts, gate structures and other features, as well as the dielectric materials therebetween, decrease to 45 nm and 32 nm, or lower, dimensions. However, the thickness of the dielectric layers remain substantially constant, resulting in increased depth to width aspect ratios of the features.
Sputtering, also known as physical vapor deposition (PVD), is a method of forming metallic features in integrated circuits. Sputtering deposits a material layer on a substrate. A source material, such as a target, is bombarded by ions strongly accelerated by an electric field to eject material from the target, which is then deposited on the substrate.
In a physical vapor deposition process, fast-moving ions strike the target, dislodging particles from the target surface. The particles may be charged by the interaction with the incident ions through a charge transfer mechanism. Alternatively, the particles may be charged through interaction with any electric fields existing in the space, or the particles may remain uncharged. Deposition generally occurs faster on field regions and near the tops of trench sidewalls. During deposition, ejected particles may travel in all directions, rather than travelling in directions generally orthogonal to the substrate surface, resulting in overhanging structures formed on the corners of the trench. Overhanging structures disposed on opposite sides of a trench or other opening may grow together, resulting in premature closing and thus preventing complete filling of the trench or opening and forming a hole or a void. When depositing conductive materials to form conductive pathways for a device, such holes or voids undesirably severely diminish the electrical conductivity of the formed feature. Moreover, the higher aspect ratios of trenches and vias in next generation devices are even harder to fill without voids.
Controlling the ion fractions or ion density reaching to the substrate surface at a certain range may improve the bottom and sidewall coverage during the metal layer deposition process. In one example, the particles dislodged from the target may be ionized and accelerated under an electrical bias applied to the substrate. The resulting narrow angular flux distribution encourages particles to travel down into the trench before early closing-up of the trench. It is believed that by increasing the ion fraction/ion density near the substrate surface may promote ion trajectories that are more orthogonal to the substrate. As accelerated ions approach the substrate surface, momentum carried from the accelerated ions may reach deeper down into the trench, whereupon they deflect toward the trench sidewall under the influence of the electrical bias. Nonetheless, the deeper penetration into the trench reduces the effect of overhang near the top of the sidewall. However, as the aspect ratios of the trenches are getting higher and substrate sizes are becoming larger, reaching down to the trench bottom is more difficult and uniformly depositing materials across the substrate surface is also more difficult. Thus, PVD processing remains a challenge to overcome the problem of overhang management.
Therefore, the inventors have provided improved methods and apparatus for forming a metal containing layer with good bottom and sidewall management.